The Challenge

Develop ultra low latency and ultra-low gate count Ethernet MAC/PCS and RS-FEC IP Cores for applications where latency is critical such as algorithmic trading.

Cores must be capable of addressing typical applications such as:

• Market Data Feed Handler and Tick-to-Trade Platforms.

• Ethernet Network Test Appliances

• Network Security Appliances

• High Performance Computing

Client: Investment Banks & HFT Firms
Location: Worldwide




The Solution

Orthogone used a holistic approach to develop multiple flavors of the Ethernet MAC/PCS to support multiple data rates and Forward Error Correction (FEC) options. A single Verilog source code platform was used to support all configurations, options and technology process nodes. This greatly simplified test, integration and regression and preserved a uniform design for all options and configurations.

Multiple design innovations in the data processing algorithms resulted in ultra-low gate count and amazing latency performances making the cores ideal for applications where latency is critical (e.g. algorithmic trading).

The Details

T-robot-100
Technology Used
  • FPGA: Xilinx (Virtex-7, UltraScale and UltraScale+)
  • FPGA: Intel (Stratix-V, Arria-10, Stratix-10)

The Result

Multiple deployments have been made for different market segments and geographic locations.