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Ethernet MAC & PCS
10-, 25-, 40-, 100-Gbps

These FPGA/ASIC IP cores are high performance 10-, 25-, 40- or 100-Gbps Ethernet media access controller (MAC) and physical coding sub-layer (PCS). All IP cores are designed using advanced techniques leading to unmatched ultra-low gate count utilization and amazing latency performances. They include a rich set of standard and advanced features, making it ideal for a large number of applications.

The IP cores are designed following the requirements of IEEE 802.3-2012.


The IP cores are provided as fully integrated MAC and PCS solutions or can be delivered as standalone MAC or PCS products.

Standard XGMII (10GbE), XLGMII (40GbE), and CGMII (100GbE) interfaces interconnect the MAC and PCS IP cores. Pre-standard 25GMII interface is used for 25-Gbps data rates.

All IP cores can support full wire line speed with a 64-byte packet length. They also support back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.

The figure below presents a block diagram of the 10-, 25-, 40- or 100-Gbps MAC + PCS IP core solution.


  • Compliant with the IEEE 802.3-2012 High Speed Ethernet Standard
  • Ethernet MAC supports the 10GbE, 25GbE, 40GbE, and 100GbE line rate with a flexible and configurable feature set
  • Highly optimized implementation resulting in very low gate count and high timing margin, even on slowest FPGA speed grade
  • Soft PCS logic interfacing to standard serial transceivers at 10.3125Gbps and 25.78125Gbps
  • Standard XGMII, 25-GMII, XLGMII, and CGMII interfaces between MAC and PCS
  • Standard 10GbE SFI, XFI external interface operating at 10.3125Gbps
  • Standard 40GbE XLAUI or 100GbE CAUI external interface consisting of serial transceiver lanes operating at 10.3125Gbps, or the CAUI-4 external interface consisting of four serial transceiver lanes operating at 25.78125Gbps.
  • Pre-standard 25GbE external interface consisting of one serial transceiver running at 25.78125Gbps
  • Supports 10GBASE-R and 25GBASE-R PHY based on 64B/66B encoding
  • Supports 40GBASE-R4, 100GBASE-R4, and 100GBASE-R10 PHY based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes.
  • Supports PCS TX to PCS RX loopback
  • Supports PCS RX to PCS TX loopback
  • Supports IDLE scramble test pattern for 40G and 100G with single error injection
  • Supports SEEDs test pattern for 10G
  • Supports block synchronization and BER monitor
  • Supports multiple lanes swapping, lane alignment and deskew
  • Reports lane mapping and lane skew
  • Supports alignment marker programmable spacing (40G/100G)
  • Supports Synchronous Ethernet (Sync-E) and multiple synchronization schemes
    • Recovered clock derived from CDR is provided to the FPGA fabric
    • Can also be configured with separate reference clocks for the Tx and Rx paths
  • Supports timestamping (Tx, Rx)
  • Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average
  • Programmable IPG length (down to 1-byte)
  • Programmable Maximum Receive Unit (MRU) and Maximum Transmission Unit (MTU)
  • High performance configurable core data path interface at 32-bit (10G), 64-bit (10G, 25G), 128-bit (40G) and 256-bit (100G). Other options available for slower data interfaces.
  • Ethernet flow control and congestion management using pause frames with programmable quanta
  • XON / XOFF Frame transmission can be triggered by host (software) interface or directly by core pause frame interface signals
  • Programmable Tx minimum packet length with enable/disable padding option
  • Programmable Rx minimum packet length
  • Tx Frame Check Sequence (FCS) computation and insertion
  • Programmable Tx FCS pass-through and corruption insertion modes
  • Programmable keep/strip Rx FCS
  • Programmable Rx FCS error detection and marking
  • Programmable Rx Preamble pass-through mode
  • Programmable custom Tx Preamble insertion on a packet basis
  • Programmable Tx and Rx large frame threshold detection
  • Programmable Tx and Rx path VLAN detection (Programmable TPID, stacked VLAN)
  • Rx Frame truncation (Frame > MRU, MII Error)
  • Tx Frame truncation (Frame > MTU)
  • Programmable Rx frame discard & marking
    • Rx Frame > MRU
    • MII Error
    • SFD, Preamble Error
    • FCS Error
    • Length field mismatch
    • Unsupported control frames
    • Pause frame
  • Configurable statistics vector and collector on transmit and receive MAC data:
    • Pause frames
    • MII Error (RMAC)
    • PCS to RMAC (Runt, Error, Drop)
    • Pause Frame
    • VLAN Detect
    • VLAN Stack
    • VLAN User Detect
    • Broadcast
    • Bad Frame
    • Multicast
    • Unicast
    • FCS Error
    • Frame Receive
    • Frame Length
    • Frame over threshold
    • Frame Long
    • Jabber
    • Frame Short
    • Segment
    • Frame size histogram
      • Frame ≤ 64, Frame 65-127, Frame 128-255, Frame 256-511, Frame 512-1023, Frame 1024-1518, Frame 1519-2047, Frame 2048-4095, Frame 4096-8191, Frame > 8191
  • Configurable statistics vector and collector on transmit and receive PCS:
    • EEE Wake Error
    • Test Pattern Error (IDLE/SEED)
    • Sync Header Error
    • Block Error
    • BIP Error (40G/100G)
  • Configurable status vector and event collector on transmit and receive PCS:
    • RX LPI Indication
    • TX LPI Indication
    • HBER
    • Block Lock
    • RX Fault
    • TX Fault
    • Align (40G/100G)
    • Alignment Marker Error (40G/100G)
    • Link Status
    • Illegal Skew (40G/100G)
    • Slip
Typical Applications

These IP cores are designed using advanced techniques leading to unmatched ultra-low gate count utilization and amazing latency performances. All cores provide a rich set of standard and advanced features, making them ideal for a large number of applications. Typical applications include:

  • Data Centers and Computing
    • Low Latency Switch
    • Network Interface Card (NIC)
    • HW Acceleration / Data Acquisition
  • Communication and Networking
    • Packet Based Processing
    • Core / Edge Routers
    • Aggregation
    • Access & Backhaul Solutions
    • Network Interface Device (NID)
    • Ethernet – Interlaken Bridge
  • Transport / Transmission
    • Ethernet – OTN Mapper
    • Transponder / Muxponder
    • Line Card / Switch-Fabric Card
  • Other Applications
    • Ethernet Traffic Monitoring
    • Test Equipment
    • Video over IP (SMPTE 2022-1,2,5,6)
    • Low-latency Ethernet Encryptors
Product brief
10G-MAC+PCS-ProductBrief [433.62 KB]
1.0 2015/10/19
25G-MAC+PCS-ProductBrief [432.55 KB]
0.1 2015/10/19
40G-MAC+PCS-ProductBrief [434.44 KB]
1.0 2015/10/19
100G-MAC+PCS-ProductBrief [434.55 KB]
1.0 2015/10/19
Data sheet
OTI-MAC-PCS-DataSheet [2.93 MB]
0.3 2015/10/01
Product Ordering Information

Part No.

IP Core Product Description



ENET-010G-S-01 10-Gbps Ethernet Integrated MAC & PCS (10GBASE-R) Telecom


Data centers
EMAC-010G-S-01 10-Gbps Ethernet MAC
EPCS-010G-S-01 10-Gbps Ethernet PCS (10GBASE-R)


ENET-040G-S-01 40-Gbps Ethernet Integrated MAC & PCS (40GBASE-R4) Telecom


Data centers
EMAC-040G-S-01 40-Gbps Ethernet MAC
EPCS-040G-S-01 40-Gbps Ethernet PCS (40GBASE-R4)


ENET-100G-S-01 100-Gbps Ethernet MAC & PCS (100GBASE-R4, 100GBASE-R10) Telecom


Data centers

EMAC-100G-S-01 100-Gbps Ethernet MAC
EPCS-100G-S-01 100-Gbps Ethernet PCS (100GBASE-R4, 100GBASE-R10)


ENET-025G-S-01 25-Gbps Ethernet Integrated MAC & PCS (25GBASE-R) (*) Telecom


Data centers
EMAC-025G-S-01 25-Gbps Ethernet MAC (*)
EPCS-025G-S-01 25-Gbps Ethernet PCS (25GBASE-R) (*)

The cores are currently provided under early access program.
(*) 25-Gbps pre-standard

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